Low power register file design by power-aware register assignment

The multi-banked register file (MBRF) is an effective approach to reduce the complexity for a monolithic register file. In order to apply the multi-banked register file to a low-power microprocessor, we have to design a dynamic voltage scaling (DVS) approach for the MBRF to reduce its power consumption. However, when the temporary values are stored into a MBRF, their distributed storage locations will make us difficultly identifying when a register bank should be powered up or powered down. To resolve this problem, in this paper, we analyze the accessed frequencies of the temporary-values in a program and cluster them into register banks by their frequencies. The major goal is to make those infrequently accessed register banks have more opportunities to stay in the idle mode. Through a proposed DVS circuit, we can then turn these infrequently-accessed register banks into a low supply-voltage to save the static power. Simulation results show that, for a four-banked register file, on average, our approach reduces about 50% energy consumption while performance loss can be limited to less than 17%, compared to a MBRF without DVS.