MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization

W. C. Lin; H. P. Huang; K. H. Kao; M. H. Chiang; D. Lu; W. C. Hsu; Y. H. Wang; W. C.Y. Ma; H. H. Tsai; Y. J. Lee; H. L. Chiang; J. F. Wang; I. Radu

doi:10.1109/ESSDERC59256.2023.10268514

MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization

W. C. Lin
, H. P. Huang
, K. H. Kao
, M. H. Chiang
, D. Lu
, W. C. Hsu
, Y. H. Wang
, W. C.Y. Ma
, H. H. Tsai
, Y. J. Lee
, H. L. Chiang
, J. F. Wang
, I. Radu

National Cheng Kung University
National Sun Yat-sen University
Taiwan Semiconductor Research Institute
Taiwan Semiconductor Manufacturing Company

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

1 引文斯高帕斯（Scopus）

摘要

Power consumption of MOSFETs leading to undesired heat has become one of the major challenges of CMOS working at cryogenic temperatures for novel applications. Although lowering temperature (T) may benefit supply voltage (VDD) scaling and power reduction, it is still unclear how the correlations between VDD and T impact the device performance and power efficiency. In this work, we present a comprehensive study on the power performance evaluation, based on the characterization of MOSFETs at different VDD within a temperature range from 300 to 10 K. Owing to the saturation of subthreshold swing, limited VDD scaling with optimal VDD(T) at T ≦ 100 K is the key to acquire higher gate overdrive voltage for the performance improvement in cryogenic conditions.

原文	英語
主出版物標題	ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference
發行者	Editions Frontieres
頁面	9-12
頁數	4
ISBN（電子）	9798350304237
DOIs	https://doi.org/10.1109/ESSDERC59256.2023.10268514
出版狀態	已出版 - 2023
對外發佈	是
事件	53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023 - Lisbon, 葡萄牙持續時間: 11 09 2023 → 14 09 2023

出版系列

名字	European Solid-State Device Research Conference
卷	2023-September
ISSN（列印）	1930-8876

Conference

Conference	53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023
國家/地區	葡萄牙
城市	Lisbon
期間	11/09/23 → 14/09/23

文獻附註

Publisher Copyright:
© 2023 IEEE.

存取文件

10.1109/ESSDERC59256.2023.10268514

其它文件與鏈接

Link to publication in Scopus

引用此

Lin, W. C., Huang, H. P., Kao, K. H., Chiang, M. H., Lu, D., Hsu, W. C., Wang, Y. H., Ma, W. C. Y., Tsai, H. H., Lee, Y. J., Chiang, H. L., Wang, J. F., & Radu, I. (2023). MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization. 於 ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (頁 9-12). (European Solid-State Device Research Conference; 卷 2023-September). Editions Frontieres. https://doi.org/10.1109/ESSDERC59256.2023.10268514

@inproceedings{94285809286e4ab4ae4d14129a20ab76,

title = "MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization",

abstract = "Power consumption of MOSFETs leading to undesired heat has become one of the major challenges of CMOS working at cryogenic temperatures for novel applications. Although lowering temperature (T) may benefit supply voltage (VDD) scaling and power reduction, it is still unclear how the correlations between VDD and T impact the device performance and power efficiency. In this work, we present a comprehensive study on the power performance evaluation, based on the characterization of MOSFETs at different VDD within a temperature range from 300 to 10 K. Owing to the saturation of subthreshold swing, limited VDD scaling with optimal VDD(T) at T ≦ 100 K is the key to acquire higher gate overdrive voltage for the performance improvement in cryogenic conditions.",

keywords = "MOSFET, subthreshold swing, supply voltage",

author = "Lin, \{W. C.\} and Huang, \{H. P.\} and Kao, \{K. H.\} and Chiang, \{M. H.\} and D. Lu and Hsu, \{W. C.\} and Wang, \{Y. H.\} and Ma, \{W. C.Y.\} and Tsai, \{H. H.\} and Lee, \{Y. J.\} and Chiang, \{H. L.\} and Wang, \{J. F.\} and I. Radu",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023 ; Conference date: 11-09-2023 Through 14-09-2023",

year = "2023",

doi = "10.1109/ESSDERC59256.2023.10268514",

language = "英语",

series = "European Solid-State Device Research Conference",

publisher = "Editions Frontieres",

pages = "9--12",

booktitle = "ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference",

}

Lin, WC, Huang, HP, Kao, KH, Chiang, MH, Lu, D, Hsu, WC, Wang, YH, Ma, WCY, Tsai, HH, Lee, YJ, Chiang, HL, Wang, JF & Radu, I 2023, MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization. 於 ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference. European Solid-State Device Research Conference, 卷 2023-September, Editions Frontieres, 頁 9-12, 53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023, Lisbon, 葡萄牙, 11/09/23. https://doi.org/10.1109/ESSDERC59256.2023.10268514

MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization. / Lin, W. C.; Huang, H. P.; Kao, K. H. 等.
ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference. Editions Frontieres, 2023. p. 9-12 (European Solid-State Device Research Conference; 卷 2023-September).

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

TY - GEN

T1 - MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization

AU - Lin, W. C.

AU - Huang, H. P.

AU - Kao, K. H.

AU - Chiang, M. H.

AU - Lu, D.

AU - Hsu, W. C.

AU - Wang, Y. H.

AU - Ma, W. C.Y.

AU - Tsai, H. H.

AU - Lee, Y. J.

AU - Chiang, H. L.

AU - Wang, J. F.

AU - Radu, I.

PY - 2023

Y1 - 2023

N2 - Power consumption of MOSFETs leading to undesired heat has become one of the major challenges of CMOS working at cryogenic temperatures for novel applications. Although lowering temperature (T) may benefit supply voltage (VDD) scaling and power reduction, it is still unclear how the correlations between VDD and T impact the device performance and power efficiency. In this work, we present a comprehensive study on the power performance evaluation, based on the characterization of MOSFETs at different VDD within a temperature range from 300 to 10 K. Owing to the saturation of subthreshold swing, limited VDD scaling with optimal VDD(T) at T ≦ 100 K is the key to acquire higher gate overdrive voltage for the performance improvement in cryogenic conditions.

AB - Power consumption of MOSFETs leading to undesired heat has become one of the major challenges of CMOS working at cryogenic temperatures for novel applications. Although lowering temperature (T) may benefit supply voltage (VDD) scaling and power reduction, it is still unclear how the correlations between VDD and T impact the device performance and power efficiency. In this work, we present a comprehensive study on the power performance evaluation, based on the characterization of MOSFETs at different VDD within a temperature range from 300 to 10 K. Owing to the saturation of subthreshold swing, limited VDD scaling with optimal VDD(T) at T ≦ 100 K is the key to acquire higher gate overdrive voltage for the performance improvement in cryogenic conditions.

KW - MOSFET

KW - subthreshold swing

KW - supply voltage

UR - https://www.scopus.com/pages/publications/85175429316

U2 - 10.1109/ESSDERC59256.2023.10268514

DO - 10.1109/ESSDERC59256.2023.10268514

M3 - 会议稿件

AN - SCOPUS:85175429316

T3 - European Solid-State Device Research Conference

SP - 9

EP - 12

BT - ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference

PB - Editions Frontieres

T2 - 53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023

Y2 - 11 September 2023 through 14 September 2023

ER -

MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization

摘要

出版系列

Conference

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指紋

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