Multi-core FPGA implementation of ECC with homogeneous Co-Z coordinate representation

Bo Yuan Peng; Yuan Che Hsu; Yu Jia Chen; Di Chia Chueh; Chen Mou Cheng; Bo Yin Yang

doi:10.1007/978-3-319-48965-0_42

Multi-core FPGA implementation of ECC with homogeneous Co-Z coordinate representation

Bo Yuan Peng^*
, Yuan Che Hsu
, Yu Jia Chen
, Di Chia Chueh
, Chen Mou Cheng
, Bo Yin Yang

^*此作品的通信作者

Academia Sinica Taiwan HQ
National Taiwan University
The University of Osaka

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

2 引文斯高帕斯（Scopus）

摘要

Elliptic Curve Cryptography is gaining popularity, and optimization opportunities exist on several different levels: algorithm, architecture, and/or implementation. To support a wide variety of curves and at the same time resist timing/power-based side-channel attacks, our scalar multiplication is implemented using the Co-Z ladder due to Hutter, Joye, and Sierra. We analyze the parallelism of the Co-Z ladder and show that a 12-core (though inefficient) system can complete a ladder step with the fastest speed. We also combine optimizations at every level in an efficient multi-core FPGA implementation. The size of the prime modulus can also be changed easily, for which we have implemented and tested up to 528-bits used in the NIST P-521 curve. Based on this building block, we have developed a multi-core architecture that supports multiple parallel modular additions, multiplications, and inverses.

原文	英語
主出版物標題	Cryptology and Network Security - 15th International Conference, CANS 2016, Proceedings
編輯	Giuseppe Persiano, Sara Foresti
發行者	Springer Verlag
頁面	637-647
頁數	11
ISBN（列印）	9783319489643
DOIs	https://doi.org/10.1007/978-3-319-48965-0_42
出版狀態	已出版 - 2016
對外發佈	是
事件	15th International Conference on Cryptology and Network Security, CANS 2016 - Milan, 意大利持續時間: 14 11 2016 → 16 11 2016

出版系列

名字	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
卷	10052 LNCS
ISSN（列印）	0302-9743
ISSN（電子）	1611-3349

Conference

Conference	15th International Conference on Cryptology and Network Security, CANS 2016
國家/地區	意大利
城市	Milan
期間	14/11/16 → 16/11/16

文獻附註

Publisher Copyright:
© Springer International Publishing AG 2016.

存取文件

10.1007/978-3-319-48965-0_42

其它文件與鏈接

Link to publication in Scopus

引用此

Peng, B. Y., Hsu, Y. C., Chen, Y. J., Chueh, D. C., Cheng, C. M., & Yang, B. Y. (2016). Multi-core FPGA implementation of ECC with homogeneous Co-Z coordinate representation. 於 G. Persiano, & S. Foresti (編輯), Cryptology and Network Security - 15th International Conference, CANS 2016, Proceedings (頁 637-647). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); 卷 10052 LNCS). Springer Verlag. https://doi.org/10.1007/978-3-319-48965-0_42

Peng, Bo Yuan ; Hsu, Yuan Che ; Chen, Yu Jia 等. / Multi-core FPGA implementation of ECC with homogeneous Co-Z coordinate representation. Cryptology and Network Security - 15th International Conference, CANS 2016, Proceedings. 編輯 / Giuseppe Persiano ; Sara Foresti. Springer Verlag, 2016. 頁 637-647 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{be79736616d34a5c82e847371d067f7c,

title = "Multi-core FPGA implementation of ECC with homogeneous Co-Z coordinate representation",

abstract = "Elliptic Curve Cryptography is gaining popularity, and optimization opportunities exist on several different levels: algorithm, architecture, and/or implementation. To support a wide variety of curves and at the same time resist timing/power-based side-channel attacks, our scalar multiplication is implemented using the Co-Z ladder due to Hutter, Joye, and Sierra. We analyze the parallelism of the Co-Z ladder and show that a 12-core (though inefficient) system can complete a ladder step with the fastest speed. We also combine optimizations at every level in an efficient multi-core FPGA implementation. The size of the prime modulus can also be changed easily, for which we have implemented and tested up to 528-bits used in the NIST P-521 curve. Based on this building block, we have developed a multi-core architecture that supports multiple parallel modular additions, multiplications, and inverses.",

keywords = "Co-Z, ECC, FPGA, Montgomery reduction, Multi-core",

author = "Peng, \{Bo Yuan\} and Hsu, \{Yuan Che\} and Chen, \{Yu Jia\} and Chueh, \{Di Chia\} and Cheng, \{Chen Mou\} and Yang, \{Bo Yin\}",

note = "Publisher Copyright: {\textcopyright} Springer International Publishing AG 2016.; 15th International Conference on Cryptology and Network Security, CANS 2016 ; Conference date: 14-11-2016 Through 16-11-2016",

year = "2016",

doi = "10.1007/978-3-319-48965-0\_42",

language = "英语",

isbn = "9783319489643",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

publisher = "Springer Verlag",

pages = "637--647",

editor = "Giuseppe Persiano and Sara Foresti",

booktitle = "Cryptology and Network Security - 15th International Conference, CANS 2016, Proceedings",

address = "德国",

}

Peng, BY, Hsu, YC, Chen, YJ, Chueh, DC, Cheng, CM & Yang, BY 2016, Multi-core FPGA implementation of ECC with homogeneous Co-Z coordinate representation. 於 G Persiano & S Foresti (編輯), Cryptology and Network Security - 15th International Conference, CANS 2016, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 卷 10052 LNCS, Springer Verlag, 頁 637-647, 15th International Conference on Cryptology and Network Security, CANS 2016, Milan, 意大利, 14/11/16. https://doi.org/10.1007/978-3-319-48965-0_42

Multi-core FPGA implementation of ECC with homogeneous Co-Z coordinate representation. / Peng, Bo Yuan; Hsu, Yuan Che; Chen, Yu Jia 等.
Cryptology and Network Security - 15th International Conference, CANS 2016, Proceedings. 編輯 / Giuseppe Persiano; Sara Foresti. Springer Verlag, 2016. p. 637-647 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); 卷 10052 LNCS).

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

TY - GEN

T1 - Multi-core FPGA implementation of ECC with homogeneous Co-Z coordinate representation

AU - Peng, Bo Yuan

AU - Hsu, Yuan Che

AU - Chen, Yu Jia

AU - Chueh, Di Chia

AU - Cheng, Chen Mou

AU - Yang, Bo Yin

N1 - Publisher Copyright: © Springer International Publishing AG 2016.

PY - 2016

Y1 - 2016

N2 - Elliptic Curve Cryptography is gaining popularity, and optimization opportunities exist on several different levels: algorithm, architecture, and/or implementation. To support a wide variety of curves and at the same time resist timing/power-based side-channel attacks, our scalar multiplication is implemented using the Co-Z ladder due to Hutter, Joye, and Sierra. We analyze the parallelism of the Co-Z ladder and show that a 12-core (though inefficient) system can complete a ladder step with the fastest speed. We also combine optimizations at every level in an efficient multi-core FPGA implementation. The size of the prime modulus can also be changed easily, for which we have implemented and tested up to 528-bits used in the NIST P-521 curve. Based on this building block, we have developed a multi-core architecture that supports multiple parallel modular additions, multiplications, and inverses.

AB - Elliptic Curve Cryptography is gaining popularity, and optimization opportunities exist on several different levels: algorithm, architecture, and/or implementation. To support a wide variety of curves and at the same time resist timing/power-based side-channel attacks, our scalar multiplication is implemented using the Co-Z ladder due to Hutter, Joye, and Sierra. We analyze the parallelism of the Co-Z ladder and show that a 12-core (though inefficient) system can complete a ladder step with the fastest speed. We also combine optimizations at every level in an efficient multi-core FPGA implementation. The size of the prime modulus can also be changed easily, for which we have implemented and tested up to 528-bits used in the NIST P-521 curve. Based on this building block, we have developed a multi-core architecture that supports multiple parallel modular additions, multiplications, and inverses.

KW - Co-Z

KW - ECC

KW - FPGA

KW - Montgomery reduction

KW - Multi-core

UR - https://www.scopus.com/pages/publications/84994817723

U2 - 10.1007/978-3-319-48965-0_42

DO - 10.1007/978-3-319-48965-0_42

M3 - 会议稿件

AN - SCOPUS:84994817723

SN - 9783319489643

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 637

EP - 647

BT - Cryptology and Network Security - 15th International Conference, CANS 2016, Proceedings

A2 - Persiano, Giuseppe

A2 - Foresti, Sara

PB - Springer Verlag

T2 - 15th International Conference on Cryptology and Network Security, CANS 2016

Y2 - 14 November 2016 through 16 November 2016

ER -

Peng BY, Hsu YC, Chen YJ, Chueh DC, Cheng CM, Yang BY. Multi-core FPGA implementation of ECC with homogeneous Co-Z coordinate representation. 於 Persiano G, Foresti S, 編輯, Cryptology and Network Security - 15th International Conference, CANS 2016, Proceedings. Springer Verlag. 2016. p. 637-647. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-319-48965-0_42

Multi-core FPGA implementation of ECC with homogeneous Co-Z coordinate representation

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