Multi-point model reductions of VLSI interconnects using the Rational Arnoldi Method with Adaptive Orders (RAMAO)

Herng Jer Lee; Chia Chi Chu; Wu Shiung Feng

Multi-point model reductions of VLSI interconnects using the Rational Arnoldi Method with Adaptive Orders (RAMAO)

Herng Jer Lee^*, Chia Chi Chu, Wu Shiung Feng

^*此作品的通信作者

Chang Gung University

研究成果: 會議稿件的類型 › 論文 › 同行評審

7 引文斯高帕斯（Scopus）

摘要

This work proposes the rational Arnoldi method with adaplive orders for high-speed VLSI interconnect reductions. It is based on an extension of the classical multi-point Padé approximation by using the rational Arnoldi iteration approach. Given a set of expansion points, the transfer function error at each expansion point is derived first. In each iteration of the propose algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. The corresponding reduced-order model yields the greatest output moment improvement.

原文	英語
頁面	1009-1012
頁數	4
出版狀態	已出版 - 2004
事件	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, 台灣持續時間: 06 12 2004 → 09 12 2004

Conference

Conference	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家/地區	台灣
城市	Tainan
期間	06/12/04 → 09/12/04

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Link to publication in Scopus

引用此

@conference{4f51177b86164d1c882b88c5eb0af959,

title = "Multi-point model reductions of VLSI interconnects using the Rational Arnoldi Method with Adaptive Orders (RAMAO)",

abstract = "This work proposes the rational Arnoldi method with adaplive orders for high-speed VLSI interconnect reductions. It is based on an extension of the classical multi-point Pad{\'e} approximation by using the rational Arnoldi iteration approach. Given a set of expansion points, the transfer function error at each expansion point is derived first. In each iteration of the propose algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. The corresponding reduced-order model yields the greatest output moment improvement.",

author = "Lee, {Herng Jer} and Chu, {Chia Chi} and Feng, {Wu Shiung}",

year = "2004",

language = "英语",

pages = "1009--1012",

note = "2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology ; Conference date: 06-12-2004 Through 09-12-2004",

}

Multi-point model reductions of VLSI interconnects using the Rational Arnoldi Method with Adaptive Orders (RAMAO). / Lee, Herng Jer; Chu, Chia Chi; Feng, Wu Shiung.
2004. 1009-1012 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, 台灣.

研究成果: 會議稿件的類型 › 論文 › 同行評審

TY - CONF

T1 - Multi-point model reductions of VLSI interconnects using the Rational Arnoldi Method with Adaptive Orders (RAMAO)

AU - Lee, Herng Jer

AU - Chu, Chia Chi

AU - Feng, Wu Shiung

PY - 2004

Y1 - 2004

N2 - This work proposes the rational Arnoldi method with adaplive orders for high-speed VLSI interconnect reductions. It is based on an extension of the classical multi-point Padé approximation by using the rational Arnoldi iteration approach. Given a set of expansion points, the transfer function error at each expansion point is derived first. In each iteration of the propose algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. The corresponding reduced-order model yields the greatest output moment improvement.

AB - This work proposes the rational Arnoldi method with adaplive orders for high-speed VLSI interconnect reductions. It is based on an extension of the classical multi-point Padé approximation by using the rational Arnoldi iteration approach. Given a set of expansion points, the transfer function error at each expansion point is derived first. In each iteration of the propose algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. The corresponding reduced-order model yields the greatest output moment improvement.

UR - http://www.scopus.com/inward/record.url?scp=21644475930&partnerID=8YFLogxK

M3 - 论文

AN - SCOPUS:21644475930

SP - 1009

EP - 1012

T2 - 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology

Y2 - 6 December 2004 through 9 December 2004

ER -

Multi-point model reductions of VLSI interconnects using the Rational Arnoldi Method with Adaptive Orders (RAMAO)

摘要

Conference

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