Novel symmetrical buffer design for VLSI applications

Hwang Cherng Chow; Wu Shiung Feng

Novel symmetrical buffer design for VLSI applications

Hwang Cherng Chow^*, Wu Shiung Feng

^*此作品的通信作者

電子工程學系(含學碩博士班)

研究成果: 會議稿件的類型 › 論文 › 同行評審

摘要

Novel fast buffers by transient part circuit technique are described in this paper. The proposed circuits are fully symmetrical in its structure, therefore design is straight forward and well balanced speed is easily obtained. As compared to prior arts [9], [1], the delay ratio of this work is over 300% and 10% balance improvement, respectively. While based on a design criterion of the same area the proposed buffer shows 27% and 76% averaged speed enhancements on propagation delays.

原文	英語
頁面	176-179
頁數	4
出版狀態	已出版 - 2000
事件	43rd Midwest Circuits and Systems Conference (MWSCAS-2000) - Lansing, MI, 美國持續時間: 08 08 2000 → 11 08 2000

Conference

Conference	43rd Midwest Circuits and Systems Conference (MWSCAS-2000)
國家/地區	美國
城市	Lansing, MI
期間	08/08/00 → 11/08/00

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引用此

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title = "Novel symmetrical buffer design for VLSI applications",

abstract = "Novel fast buffers by transient part circuit technique are described in this paper. The proposed circuits are fully symmetrical in its structure, therefore design is straight forward and well balanced speed is easily obtained. As compared to prior arts [9], [1], the delay ratio of this work is over 300% and 10% balance improvement, respectively. While based on a design criterion of the same area the proposed buffer shows 27% and 76% averaged speed enhancements on propagation delays.",

author = "Chow, {Hwang Cherng} and Feng, {Wu Shiung}",

year = "2000",

language = "英语",

pages = "176--179",

note = "43rd Midwest Circuits and Systems Conference (MWSCAS-2000) ; Conference date: 08-08-2000 Through 11-08-2000",

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TY - CONF

T1 - Novel symmetrical buffer design for VLSI applications

AU - Chow, Hwang Cherng

AU - Feng, Wu Shiung

PY - 2000

Y1 - 2000

N2 - Novel fast buffers by transient part circuit technique are described in this paper. The proposed circuits are fully symmetrical in its structure, therefore design is straight forward and well balanced speed is easily obtained. As compared to prior arts [9], [1], the delay ratio of this work is over 300% and 10% balance improvement, respectively. While based on a design criterion of the same area the proposed buffer shows 27% and 76% averaged speed enhancements on propagation delays.

AB - Novel fast buffers by transient part circuit technique are described in this paper. The proposed circuits are fully symmetrical in its structure, therefore design is straight forward and well balanced speed is easily obtained. As compared to prior arts [9], [1], the delay ratio of this work is over 300% and 10% balance improvement, respectively. While based on a design criterion of the same area the proposed buffer shows 27% and 76% averaged speed enhancements on propagation delays.

UR - http://www.scopus.com/inward/record.url?scp=0034465267&partnerID=8YFLogxK

M3 - 论文

AN - SCOPUS:0034465267

SP - 176

EP - 179

T2 - 43rd Midwest Circuits and Systems Conference (MWSCAS-2000)

Y2 - 8 August 2000 through 11 August 2000

ER -

Novel symmetrical buffer design for VLSI applications

摘要

Conference

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