TY - JOUR
T1 - Novel VLSI architecture for a variable-length key, 64-bit BLOWFISH block cipher
AU - Lai, Yeong Kang
AU - Shu, Yu Chuan
PY - 1999
Y1 - 1999
N2 - In this paper, a novel one-round VLSI architecture of the block cipher, BLOWFISH, for data encryption/decryption has been presented. Based on pipelined structure, efficient key management, and the mapping of the algorithm onto the datapath the performance of the architecture can be increased. In addition, all important standardized modes of operation of block ciphers, such as ECB, CBC, and OFB, are also supported. Due to the properties of low cost, high throughput rate, and scalable encryption, the VLSI block cipher provides efficient solutions for data encryption like wireless communication applications.
AB - In this paper, a novel one-round VLSI architecture of the block cipher, BLOWFISH, for data encryption/decryption has been presented. Based on pipelined structure, efficient key management, and the mapping of the algorithm onto the datapath the performance of the architecture can be increased. In addition, all important standardized modes of operation of block ciphers, such as ECB, CBC, and OFB, are also supported. Due to the properties of low cost, high throughput rate, and scalable encryption, the VLSI block cipher provides efficient solutions for data encryption like wireless communication applications.
UR - http://www.scopus.com/inward/record.url?scp=0033313966&partnerID=8YFLogxK
M3 - 会议文章
AN - SCOPUS:0033313966
SN - 1520-6130
SP - 568
EP - 577
JO - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
JF - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
T2 - 1999 IEEE Workshop on SiGNAL Processing Systems (SiPS 99): 'Design and Implementation'
Y2 - 20 October 1999 through 22 October 1999
ER -