TY - JOUR
T1 - Novel VLSI architecture for Lempel-Ziv based data compression
AU - Lai, Yeong Kang
AU - Chen, Kuo Chen
PY - 2000
Y1 - 2000
N2 - In this paper, a novel VLSI architecture for Lempel-Ziv-based data compression/decompression is presented. Based on the efficient data flow, the proposed architecture can fully exploit the data-reuse to decrease external memory accesses and reduce the pin count. In addition, Parameters of the architecture such as the sliding window size, the dictionary size, and the symbol word-length, can be changed to suit the application. The proposed architecture is a high throughput and cost-effective architecture, and very suitable for wireless communication application.
AB - In this paper, a novel VLSI architecture for Lempel-Ziv-based data compression/decompression is presented. Based on the efficient data flow, the proposed architecture can fully exploit the data-reuse to decrease external memory accesses and reduce the pin count. In addition, Parameters of the architecture such as the sliding window size, the dictionary size, and the symbol word-length, can be changed to suit the application. The proposed architecture is a high throughput and cost-effective architecture, and very suitable for wireless communication application.
UR - http://www.scopus.com/inward/record.url?scp=0033702731&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2000.857523
DO - 10.1109/ISCAS.2000.857523
M3 - 会议文章
AN - SCOPUS:0033702731
SN - 0271-4310
VL - 5
SP - V-617-V-620
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000
Y2 - 28 May 2000 through 31 May 2000
ER -