On fault-tolerant FFT butterfly network design

Shyue Kung Lu; Cheng Wen Wu; Sy Yen Kuo

On fault-tolerant FFT butterfly network design

Shyue Kung Lu^*
, Cheng Wen Wu
, Sy Yen Kuo

^*此作品的通信作者

Loong Hua Inst of Technology &

研究成果: 期刊稿件 › 會議文章 › 同行評審

4 引文斯高帕斯（Scopus）

摘要

We present novel fault-tolerant methods for FFT processors. A reconfiguration mechanism is used to bypass the faulty cell. Special cell designs are presented which implement the reconfiguration algorithm. The reliability of the FFT system increases significantly, with about 16% and 25% hardware overhead for the bit-level and module-level designs, respectively.

原文	英語
頁（從 - 到）	69-72
頁數	4
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	2
出版狀態	已出版 - 1996
對外發佈	是
事件	Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA 持續時間: 12 05 1996 → 15 05 1996

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引用此

@article{6752db6b7d284a79a125ec33ae3800ff,

title = "On fault-tolerant FFT butterfly network design",

abstract = "We present novel fault-tolerant methods for FFT processors. A reconfiguration mechanism is used to bypass the faulty cell. Special cell designs are presented which implement the reconfiguration algorithm. The reliability of the FFT system increases significantly, with about 16\% and 25\% hardware overhead for the bit-level and module-level designs, respectively.",

author = "Lu, \{Shyue Kung\} and Wu, \{Cheng Wen\} and Kuo, \{Sy Yen\}",

year = "1996",

language = "英语",

volume = "2",

pages = "69--72",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) ; Conference date: 12-05-1996 Through 15-05-1996",

}

TY - JOUR

T1 - On fault-tolerant FFT butterfly network design

AU - Lu, Shyue Kung

AU - Wu, Cheng Wen

AU - Kuo, Sy Yen

PY - 1996

Y1 - 1996

N2 - We present novel fault-tolerant methods for FFT processors. A reconfiguration mechanism is used to bypass the faulty cell. Special cell designs are presented which implement the reconfiguration algorithm. The reliability of the FFT system increases significantly, with about 16% and 25% hardware overhead for the bit-level and module-level designs, respectively.

AB - We present novel fault-tolerant methods for FFT processors. A reconfiguration mechanism is used to bypass the faulty cell. Special cell designs are presented which implement the reconfiguration algorithm. The reliability of the FFT system increases significantly, with about 16% and 25% hardware overhead for the bit-level and module-level designs, respectively.

UR - https://www.scopus.com/pages/publications/0029717585

M3 - 会议文章

AN - SCOPUS:0029717585

SN - 0271-4310

VL - 2

SP - 69

EP - 72

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4)

Y2 - 12 May 1996 through 15 May 1996

ER -

On fault-tolerant FFT butterfly network design

摘要

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