Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

Woei Cherng Wu; Tien Sheng Chao; Wu Chin Peng; Wen Luh Yang; Jian Hao Chen; Ming Wen Ma; Chao Sung Lai; Tsung Yu Yang; Chien Hsing Lee; Tsung Min Hsieh; Jhyy Cheng Liou; Tzu Ping Chen; Chien Hung Chen; Chih Hung Lin; Hwi Huang Chen; Joe Ko

doi:10.1088/0268-1242/23/1/015004

Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

Woei Cherng Wu^*, Tien Sheng Chao, Wu Chin Peng, Wen Luh Yang, Jian Hao Chen, Ming Wen Ma, Chao Sung Lai, Tsung Yu Yang, Chien Hsing Lee, Tsung Min Hsieh, Jhyy Cheng Liou, Tzu Ping Chen, Chien Hung Chen, Chih Hung Lin, Hwi Huang Chen, Joe Ko

^*此作品的通信作者

電子工程學系(含學碩博士班)

研究成果: 期刊稿件 › 文章 › 同行評審

4 引文斯高帕斯（Scopus）

摘要

In this paper, highly reliable wrapped-select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good V_TH distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 νs/5 ms) and low programming current (3.5 νA) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.

原文	英語
文章編號	015004
期刊	Semiconductor Science and Technology
卷	23
發行號	1
DOIs	https://doi.org/10.1088/0268-1242/23/1/015004
出版狀態	已出版 - 01 01 2008

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Wu, W. C., Chao, T. S., Peng, W. C., Yang, W. L., Chen, J. H., Ma, M. W., Lai, C. S., Yang, T. Y., Lee, C. H., Hsieh, T. M., Liou, J. C., Chen, T. P., Chen, C. H., Lin, C. H., Chen, H. H., & Ko, J. (2008). Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory. Semiconductor Science and Technology, 23(1), 文章 015004. https://doi.org/10.1088/0268-1242/23/1/015004

@article{1e6274451db745d0ad1910aed2785e0a,

title = "Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory",

abstract = "In this paper, highly reliable wrapped-select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good VTH distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 νs/5 ms) and low programming current (3.5 νA) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.",

author = "Wu, \{Woei Cherng\} and Chao, \{Tien Sheng\} and Peng, \{Wu Chin\} and Yang, \{Wen Luh\} and Chen, \{Jian Hao\} and Ma, \{Ming Wen\} and Lai, \{Chao Sung\} and Yang, \{Tsung Yu\} and Lee, \{Chien Hsing\} and Hsieh, \{Tsung Min\} and Liou, \{Jhyy Cheng\} and Chen, \{Tzu Ping\} and Chen, \{Chien Hung\} and Lin, \{Chih Hung\} and Chen, \{Hwi Huang\} and Joe Ko",

year = "2008",

month = jan,

day = "1",

doi = "10.1088/0268-1242/23/1/015004",

language = "英语",

volume = "23",

journal = "Semiconductor Science and Technology",

issn = "0268-1242",

publisher = "IOP Publishing Ltd.",

number = "1",

}

Wu, WC, Chao, TS, Peng, WC, Yang, WL, Chen, JH, Ma, MW, Lai, CS, Yang, TY, Lee, CH, Hsieh, TM, Liou, JC, Chen, TP, Chen, CH, Lin, CH, Chen, HH & Ko, J 2008, 'Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory', Semiconductor Science and Technology, 卷 23, 編號 1, 015004. https://doi.org/10.1088/0268-1242/23/1/015004

TY - JOUR

T1 - Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

AU - Wu, Woei Cherng

AU - Chao, Tien Sheng

AU - Peng, Wu Chin

AU - Yang, Wen Luh

AU - Chen, Jian Hao

AU - Ma, Ming Wen

AU - Lai, Chao Sung

AU - Yang, Tsung Yu

AU - Lee, Chien Hsing

AU - Hsieh, Tsung Min

AU - Liou, Jhyy Cheng

AU - Chen, Tzu Ping

AU - Chen, Chien Hung

AU - Lin, Chih Hung

AU - Chen, Hwi Huang

AU - Ko, Joe

PY - 2008/1/1

Y1 - 2008/1/1

N2 - In this paper, highly reliable wrapped-select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good VTH distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 νs/5 ms) and low programming current (3.5 νA) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.

AB - In this paper, highly reliable wrapped-select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good VTH distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 νs/5 ms) and low programming current (3.5 νA) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.

UR - http://www.scopus.com/inward/record.url?scp=37249052837&partnerID=8YFLogxK

U2 - 10.1088/0268-1242/23/1/015004

DO - 10.1088/0268-1242/23/1/015004

M3 - 文章

AN - SCOPUS:37249052837

SN - 0268-1242

VL - 23

JO - Semiconductor Science and Technology

JF - Semiconductor Science and Technology

IS - 1

M1 - 015004

ER -

Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

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