摘要
Subcircuit Extraction plays an important role in Computer-Aided-Design of digital circuits. With the rapid growth of wafer processing technologies, the integration is from very large scale to giga large scale. Therefore, to extract sub circuits from such large scale integration is computation-consuming problem. In this paper, we propose a parallel sub circuit extraction algorithm on graphic processing unit. The experimental result shows that the proposed algorithm can achieve over 3x-7x times faster than serial algorithm.
原文 | 英語 |
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主出版物標題 | Proceedings - 16th IEEE International Conference on High Performance Computing and Communications, HPCC 2014, 11th IEEE International Conference on Embedded Software and Systems, ICESS 2014 and 6th International Symposium on Cyberspace Safety and Security, CSS 2014 |
發行者 | Institute of Electrical and Electronics Engineers Inc. |
頁面 | 1248-1252 |
頁數 | 5 |
ISBN(電子) | 9781479961238 |
DOIs | |
出版狀態 | 已出版 - 09 03 2014 |
對外發佈 | 是 |
事件 | 16th IEEE International Conference on High Performance Computing and Communications, HPCC 2014, 11th IEEE International Conference on Embedded Software and Systems, ICESS 2014 and 6th International Symposium on Cyberspace Safety and Security, CSS 2014 - Paris, 法國 持續時間: 20 08 2014 → 22 08 2014 |
出版系列
名字 | Proceedings - 16th IEEE International Conference on High Performance Computing and Communications, HPCC 2014, 11th IEEE International Conference on Embedded Software and Systems, ICESS 2014 and 6th International Symposium on Cyberspace Safety and Security, CSS 2014 |
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Conference
Conference | 16th IEEE International Conference on High Performance Computing and Communications, HPCC 2014, 11th IEEE International Conference on Embedded Software and Systems, ICESS 2014 and 6th International Symposium on Cyberspace Safety and Security, CSS 2014 |
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國家/地區 | 法國 |
城市 | Paris |
期間 | 20/08/14 → 22/08/14 |
文獻附註
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