@inproceedings{2c11cb51607d4539a2a864397f332c1f,
title = "Pulsewidth control loop with low control voltage ripple",
abstract = "A pulsewidth control loop (PWCL) with low control voltage ripple is proposed in this paper. The charge pump circuit with charge sharing circuit decreases the ripple of control voltage. By decreasing the control voltage ripple for reducing the stability problem of the loop. The jitter of the output clock is reduced due to the low control voltage ripple. It is demonstrated by simulation results in a 0.18pm CMOS process. The simulation shows that the frequency range of input signal is from 100MHz to 1GHz, the duty cycle range of the input signal is from 40\% to 60\%. The proposed circuit can reduce the output clock jitters by 37.7\% and 50.6\% for the 1GHz and 100MHz,respectiveIy.",
keywords = "Duty cycle corrector (DCC), Fast locking, Lock detector, Low jitter, Pulsewidth control loops (PWCL)",
author = "Kao, \{Shao Ku\} and You, \{Yong De\}",
year = "2012",
language = "英语",
isbn = "9789881925190",
series = "Lecture Notes in Engineering and Computer Science",
publisher = "Newswood Limited",
pages = "1075--1077",
booktitle = "International MultiConference of Engineers and Computer Scientists, IMECS 2012",
note = "2012 International MultiConference of Engineers and Computer Scientists, IMECS 2012 ; Conference date: 14-03-2012 Through 16-03-2012",
}