Quantum boolean circuit construction and layout under locality constraint

I. Ming Tsai; Sy Yen Kuo

doi:10.1109/NANO.2001.966403

Quantum boolean circuit construction and layout under locality constraint

I. Ming Tsai
, Sy Yen Kuo

National Taiwan University

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

19 引文斯高帕斯（Scopus）

摘要

The discovery of Shor's prime factorization and Grover's fast database search algorithm have made quantum computing the most rapidly expanding research field recently. Nanotechnology, in particular silicon-based nanoscale device, has been proposed as one of the candidates that can be used to implement a quantum computer. In this paper, we have derived a systematic procedure to realize any general m-to-n bit combinational boolean logic using elementary quantum gates. The quantum circuit layout under the locality constraint is then formulated, together with the gate count evaluation function, to reduce the total number of quantum gates required to implement the circuit.

原文	英語
主出版物標題	Proceedings of the 2001 1st IEEE Conference on Nanotechnology, IEEE-NANO 2001
發行者	IEEE Computer Society
頁面	111-116
頁數	6
ISBN（電子）	0780372158
DOIs	https://doi.org/10.1109/NANO.2001.966403
出版狀態	已出版 - 2001
對外發佈	是
事件	1st IEEE Conference on Nanotechnology, IEEE-NANO 2001 - Maui, 美國持續時間: 28 10 2001 → 30 10 2001

出版系列

名字	Proceedings of the IEEE Conference on Nanotechnology
卷	2001-January
ISSN（列印）	1944-9399
ISSN（電子）	1944-9380

Conference

Conference	1st IEEE Conference on Nanotechnology, IEEE-NANO 2001
國家/地區	美國
城市	Maui
期間	28/10/01 → 30/10/01

文獻附註

Publisher Copyright:
© 2001 IEEE.

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10.1109/NANO.2001.966403

其它文件與鏈接

Link to publication in Scopus

引用此

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title = "Quantum boolean circuit construction and layout under locality constraint",

abstract = "The discovery of Shor's prime factorization and Grover's fast database search algorithm have made quantum computing the most rapidly expanding research field recently. Nanotechnology, in particular silicon-based nanoscale device, has been proposed as one of the candidates that can be used to implement a quantum computer. In this paper, we have derived a systematic procedure to realize any general m-to-n bit combinational boolean logic using elementary quantum gates. The quantum circuit layout under the locality constraint is then formulated, together with the gate count evaluation function, to reduce the total number of quantum gates required to implement the circuit.",

author = "Tsai, \{I. Ming\} and Kuo, \{Sy Yen\}",

note = "Publisher Copyright: {\textcopyright} 2001 IEEE.; 1st IEEE Conference on Nanotechnology, IEEE-NANO 2001 ; Conference date: 28-10-2001 Through 30-10-2001",

year = "2001",

doi = "10.1109/NANO.2001.966403",

language = "英语",

series = "Proceedings of the IEEE Conference on Nanotechnology",

publisher = "IEEE Computer Society",

pages = "111--116",

booktitle = "Proceedings of the 2001 1st IEEE Conference on Nanotechnology, IEEE-NANO 2001",

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}

Tsai, IM & Kuo, SY 2001, Quantum boolean circuit construction and layout under locality constraint. 於 Proceedings of the 2001 1st IEEE Conference on Nanotechnology, IEEE-NANO 2001., 966403, Proceedings of the IEEE Conference on Nanotechnology, 卷 2001-January, IEEE Computer Society, 頁 111-116, 1st IEEE Conference on Nanotechnology, IEEE-NANO 2001, Maui, 美國, 28/10/01. https://doi.org/10.1109/NANO.2001.966403

Quantum boolean circuit construction and layout under locality constraint. / Tsai, I. Ming; Kuo, Sy Yen.
Proceedings of the 2001 1st IEEE Conference on Nanotechnology, IEEE-NANO 2001. IEEE Computer Society, 2001. p. 111-116 966403 (Proceedings of the IEEE Conference on Nanotechnology; 卷 2001-January).

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

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AB - The discovery of Shor's prime factorization and Grover's fast database search algorithm have made quantum computing the most rapidly expanding research field recently. Nanotechnology, in particular silicon-based nanoscale device, has been proposed as one of the candidates that can be used to implement a quantum computer. In this paper, we have derived a systematic procedure to realize any general m-to-n bit combinational boolean logic using elementary quantum gates. The quantum circuit layout under the locality constraint is then formulated, together with the gate count evaluation function, to reduce the total number of quantum gates required to implement the circuit.

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ER -

Quantum boolean circuit construction and layout under locality constraint

摘要

出版系列

Conference

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其它文件與鏈接

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