Recursive implementation of multiple delayed signal cancellation operators and their applications in pre-filtered and in-loop filtered PLLs under adverse grid conditions

Phase-Iocked loops (PLLs) are widely utilized for grid synchronization and control of power electronic converters. More recently, both in-loop filtered and pre-filtered based PLLs have become more popular due to their prompt and accurate estimations of grid voltage quantities. In the past, an advanced filters based on multiple delayed signal cancellation (MDSC) operators, have been successfully investigated in both a l'1-frame and dq-frame for extracting fundamental-frequency positive-sequence (FFPS) grid voltage quantities by using conventional synchronous reference frame (SRF)-PLL. These operators can provide more flexibility to configure the delay time and undesired harmonics in comparison with the existing cascaded delayed signal cancellation (CDSC) operators. This paper will extend their digital implementations from direct-form realizations to recursive-form realizations. With the recursive-form MDSC implementations, both pre-filtered MDSC-PLL and in-loop filtered MDSC-PLL will be investigated in details. Design guidelines of these PLLs are also outlined. Comparison studies of these two proposed PLLs and the validation of their dynamic performances are done by experimental verifications.