Saving register-file leakage power by monitoring instruction sequence in ROB

Modern portable or embedded systems support more and more complex applications. These applications make embedded devices require not only low power-consumption, but also high computing performance. To enhance performance while hold energy constraints, some high-end embedded processors, therefore, adopt conventional features to exploit instruction-level parallelism and increase clock rates. The reorder buffer (ROB) and the register file are the two most critical components to implement these features. The cooperation of them, however, causes serious leakage power, especially for a large register file. In this paper, we propose a pure hardware approach to reduce the leakage power for the register file, such that more complex features (e.g., out-of-order execution, speculation execution, etc) can be applied to high-end embedded processors. In the proposed approach, we design a monitoring scheme in the pipeline datapath to identify the timing of powering up or powering down a register. Simulation results show that our approach saves at least 50% power consumption of the register file, with almost negligible performance lost.