Selective Pruning of Sparsity-Supported Energy-Efficient Accelerator for Convolutional Neural Networks

Convolutional Neural Networks (CNNs) are widely used in various fields with the rapid development of Deep Learning (DL). However, the massive amount of parameters and huge models severely limit the calculation speed and performance of the model. To address this, model compression has become one of the most popular methods, and quantization and pruning are two of the most common techniques. Quantization reduces the bit width in exchange for lower power consumption and computing time, while pruning reduces the number of parameters to reduce memory access and operation time. However, the existing hardware architecture is still unable to satisfy real-time and low power consumption requirements simultaneously. Therefore, scholars have been paying attention to Application Specific Integrated Circuits (ASICs) and low-bit quantization co-optimization. This paper aims to co-design sparsity and quantization energy-saving accelerators. It uses the characteristics of selective pruning to design low-cost sparsity hardware and employs low-cost comparison circuits to solve the problem of energy-saving data flow dependencies and improve traditional low-efficiency non-real-time methods. In terms of hardware, compared to Dynamic Region-based Quantization (DRQ), one of the state-of-the-art hardware accelerators, the proposed network reduces the area by 43.22%, power consumption by 52.17%, and computing time by 25.36%. Additionally, it increases power efficiency by 1.29 times.