Simple and hardware-efficient row-based direct-mapping estimators in fixed-width modified Booth multipliers

The great demand of high-performance fixed-width two's-complement modified Booth multipliers (FWBM) arises because of the wide applications of approximate computing. In this paper, a row-based direct-mapping (RDM) method for designing error estimators in FWBM is proposed. The proposed closed form is derived from probability summation of each entire row to avoid the long setup time of exhaustive simulations. Consequently, a simple and systematic procedure by the Karnaugh map can be utilized to design low-error and hardware-efficient compensation circuits for various widths of FWBMs. By checking the leading column of the truncation part, the extendable design principle can be easily applied to different lengths and different columns inspected. We use Synopsys Design Compiler and TSMC 90 nm standard cell library to synthesize the register transfer language (RTL) design of our proposed estimators. In addition, the RDM is synthesized using the Xilinx Vivado tool with Xilinx Kintex-7 XC7K325T-2FFG900C FPGA. Results of software simulation, hardware synthesis, and implementation experiment validate the high accuracy, hardware saving, and power efficiency of the proposed RDM estimators.