Soft-error tolerant design in near-threshold-voltage computing

I. Chyn Wey; Si Zhan Fang; Heng Jui Chou; Zhan You Wu

doi:10.1109/ICASI.2018.8394533

Soft-error tolerant design in near-threshold-voltage computing

I. Chyn Wey, Si Zhan Fang, Heng Jui Chou, Zhan You Wu

電機工程學系(含學碩博士班及碩士在職專班)

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

2 引文斯高帕斯（Scopus）

摘要

In the advanced CMOS VLSI designs, lower supply voltage and smaller transistor lead to critical design challenges in dealing with soft-error interference, especial for the deisgn operating under near-threshold voltage. Some possible near-threshold voltage SEU-tolerant and SET-tolerant circuit design methods are discussed in this paper, such as robust C-element, Dual-Modular-Redundancy, Error-Correction with Duplication, and Error-Correction-with-shift-Timing-Output designs.

原文	英語
主出版物標題	Proceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018
編輯	Artde Donald Kin-Tak Lam, Stephen D. Prior, Teen-Hang Meen
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	1308-1309
頁數	2
ISBN（電子）	9781538643426
DOIs	https://doi.org/10.1109/ICASI.2018.8394533
出版狀態	已出版 - 22 06 2018
事件	4th IEEE International Conference on Applied System Innovation, ICASI 2018 - Chiba, 日本持續時間: 13 04 2018 → 17 04 2018

出版系列

名字	Proceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018

Conference

Conference	4th IEEE International Conference on Applied System Innovation, ICASI 2018
國家/地區	日本
城市	Chiba
期間	13/04/18 → 17/04/18

文獻附註

Publisher Copyright:
© 2018 IEEE.

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10.1109/ICASI.2018.8394533

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Link to publication in Scopus

引用此

Wey, I. C., Fang, S. Z., Chou, H. J., & Wu, Z. Y. (2018). Soft-error tolerant design in near-threshold-voltage computing. 於 A. D. K.-T. Lam, S. D. Prior, & T.-H. Meen (編輯), Proceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018 (頁 1308-1309). (Proceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICASI.2018.8394533

Wey, I. Chyn ; Fang, Si Zhan ; Chou, Heng Jui 等. / Soft-error tolerant design in near-threshold-voltage computing. Proceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018. 編輯 / Artde Donald Kin-Tak Lam ; Stephen D. Prior ; Teen-Hang Meen. Institute of Electrical and Electronics Engineers Inc., 2018. 頁 1308-1309 (Proceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018).

@inproceedings{c23d1dfbc25f45b28da3e5191a822e78,

title = "Soft-error tolerant design in near-threshold-voltage computing",

abstract = "In the advanced CMOS VLSI designs, lower supply voltage and smaller transistor lead to critical design challenges in dealing with soft-error interference, especial for the deisgn operating under near-threshold voltage. Some possible near-threshold voltage SEU-tolerant and SET-tolerant circuit design methods are discussed in this paper, such as robust C-element, Dual-Modular-Redundancy, Error-Correction with Duplication, and Error-Correction-with-shift-Timing-Output designs.",

author = "Wey, {I. Chyn} and Fang, {Si Zhan} and Chou, {Heng Jui} and Wu, {Zhan You}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 4th IEEE International Conference on Applied System Innovation, ICASI 2018 ; Conference date: 13-04-2018 Through 17-04-2018",

year = "2018",

month = jun,

day = "22",

doi = "10.1109/ICASI.2018.8394533",

language = "英语",

series = "Proceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1308--1309",

editor = "Lam, {Artde Donald Kin-Tak} and Prior, {Stephen D.} and Teen-Hang Meen",

booktitle = "Proceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018",

address = "美国",

}

Wey, IC, Fang, SZ, Chou, HJ & Wu, ZY 2018, Soft-error tolerant design in near-threshold-voltage computing. 於 ADK-T Lam, SD Prior & T-H Meen (編輯), Proceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018. Proceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018, Institute of Electrical and Electronics Engineers Inc., 頁 1308-1309, 4th IEEE International Conference on Applied System Innovation, ICASI 2018, Chiba, 日本, 13/04/18. https://doi.org/10.1109/ICASI.2018.8394533

Soft-error tolerant design in near-threshold-voltage computing. / Wey, I. Chyn; Fang, Si Zhan; Chou, Heng Jui 等.
Proceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018. 編輯 / Artde Donald Kin-Tak Lam; Stephen D. Prior; Teen-Hang Meen. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1308-1309 (Proceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018).

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

TY - GEN

T1 - Soft-error tolerant design in near-threshold-voltage computing

AU - Wey, I. Chyn

AU - Fang, Si Zhan

AU - Chou, Heng Jui

AU - Wu, Zhan You

PY - 2018/6/22

Y1 - 2018/6/22

N2 - In the advanced CMOS VLSI designs, lower supply voltage and smaller transistor lead to critical design challenges in dealing with soft-error interference, especial for the deisgn operating under near-threshold voltage. Some possible near-threshold voltage SEU-tolerant and SET-tolerant circuit design methods are discussed in this paper, such as robust C-element, Dual-Modular-Redundancy, Error-Correction with Duplication, and Error-Correction-with-shift-Timing-Output designs.

AB - In the advanced CMOS VLSI designs, lower supply voltage and smaller transistor lead to critical design challenges in dealing with soft-error interference, especial for the deisgn operating under near-threshold voltage. Some possible near-threshold voltage SEU-tolerant and SET-tolerant circuit design methods are discussed in this paper, such as robust C-element, Dual-Modular-Redundancy, Error-Correction with Duplication, and Error-Correction-with-shift-Timing-Output designs.

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U2 - 10.1109/ICASI.2018.8394533

DO - 10.1109/ICASI.2018.8394533

M3 - 会议稿件

AN - SCOPUS:85050308184

T3 - Proceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018

SP - 1308

EP - 1309

BT - Proceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018

A2 - Lam, Artde Donald Kin-Tak

A2 - Prior, Stephen D.

A2 - Meen, Teen-Hang

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 4th IEEE International Conference on Applied System Innovation, ICASI 2018

Y2 - 13 April 2018 through 17 April 2018

ER -

Wey IC, Fang SZ, Chou HJ, Wu ZY. Soft-error tolerant design in near-threshold-voltage computing. 於 Lam ADKT, Prior SD, Meen TH, 編輯, Proceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1308-1309. (Proceedings of 4th IEEE International Conference on Applied System Innovation 2018, ICASI 2018). doi: 10.1109/ICASI.2018.8394533

Soft-error tolerant design in near-threshold-voltage computing

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