Speed-enhanced CMOS level shifting circuits for VLSI applications

Speed-enhanced CMOS level shifting circuits are proposed for mixed voltage applications. In circuits embodying this invention, the main advantage as compared to the prior art is one more pair path to charge and discharge the output nodes simultaneously, which leads to a less PMOS to NMOS ratio problem. Therefore, the output low-to-high transition becomes faster due to charging enhancement in the initial phase. The high-to-low transition also becomes faster because of discharging enhancement in the transition period.