Superior improvements in GIDL and retention by fluorine implantation in saddle-fin array devices for sub-40-nm DRAM technology

Chia Ming Yang, Jer Chyi Wang, Wei Ping Lee, Chien Chi Lee, Chih Hung Lin, Chung Yuan Lee, Jo Hui Lin, Hsin Huei Chen, Chih Yuan Hsiao, Ruey Dar Chang, Chao Sung Lai

研究成果: 期刊稿件文章同行評審

11 引文 斯高帕斯(Scopus)

摘要

A highly improved method to reduce gate-induced drain leakage and retention fail bit counts is proposed for use in the sub-40-nm dynamic random access memory technologies. Fluorine (F) implantation with different dose post-gate oxidation is used for investigating the performance of saddle-fin (S-Fin) array devices. Significantly lower retention fail counts of 35% are achieved in the S-Fin device using a medium dosage of F implantation. Random telegraph signal-like fluctuation can also be improved using the proposed F implantation method. Trap passivation by F atoms in the source and the drain areas could have led to the improvements seen in the experiments.

原文英語
文章編號6553604
頁(從 - 到)1124-1126
頁數3
期刊IEEE Electron Device Letters
34
發行號9
DOIs
出版狀態已出版 - 2013

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