Techniques to reduce synchronization in distributed parallel logic simulation

Kai Hui Chang; Wei Ting Tu; Han Wei Wang; Yi Jong Yeh; Sy Yen Kuo

Techniques to reduce synchronization in distributed parallel logic simulation

Kai Hui Chang^*
, Wei Ting Tu
, Han Wei Wang
, Yi Jong Yeh
, Sy Yen Kuo

^*此作品的通信作者

Avery Design Systems, Inc.
National Taiwan University

研究成果: 期刊稿件 › 會議文章 › 同行評審

2 引文斯高帕斯（Scopus）

摘要

As the complexity of chip designs increase, simulation time also increases. Unit and variable delay simulation takes the most simulation time in IC design process; however, parallel processing performs inefficiently due to large amount of synchronization. In this paper, techniques to reduce the number of synchronization points in synchronous designs are proposed, and a partitioner to partition designs along flip-flop boundaries is also proposed so that these techniques can be employed on real designs.

原文	英語
文章編號	439-179
頁（從 - 到）	404-409
頁數	6
期刊	Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems
卷	16
出版狀態	已出版 - 2004
對外發佈	是
事件	Proceedings of the 16th IASTED International Conference on Parallel and Distributed Computing and Systems - Cambridge, MA, 美國持續時間: 09 11 2004 → 11 11 2004

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Link to publication in Scopus

引用此

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title = "Techniques to reduce synchronization in distributed parallel logic simulation",

abstract = "As the complexity of chip designs increase, simulation time also increases. Unit and variable delay simulation takes the most simulation time in IC design process; however, parallel processing performs inefficiently due to large amount of synchronization. In this paper, techniques to reduce the number of synchronization points in synchronous designs are proposed, and a partitioner to partition designs along flip-flop boundaries is also proposed so that these techniques can be employed on real designs.",

keywords = "Distributed parallel simulation and synchronization",

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note = "Proceedings of the 16th IASTED International Conference on Parallel and Distributed Computing and Systems ; Conference date: 09-11-2004 Through 11-11-2004",

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TY - JOUR

T1 - Techniques to reduce synchronization in distributed parallel logic simulation

AU - Chang, Kai Hui

AU - Tu, Wei Ting

AU - Wang, Han Wei

AU - Yeh, Yi Jong

AU - Kuo, Sy Yen

PY - 2004

Y1 - 2004

N2 - As the complexity of chip designs increase, simulation time also increases. Unit and variable delay simulation takes the most simulation time in IC design process; however, parallel processing performs inefficiently due to large amount of synchronization. In this paper, techniques to reduce the number of synchronization points in synchronous designs are proposed, and a partitioner to partition designs along flip-flop boundaries is also proposed so that these techniques can be employed on real designs.

AB - As the complexity of chip designs increase, simulation time also increases. Unit and variable delay simulation takes the most simulation time in IC design process; however, parallel processing performs inefficiently due to large amount of synchronization. In this paper, techniques to reduce the number of synchronization points in synchronous designs are proposed, and a partitioner to partition designs along flip-flop boundaries is also proposed so that these techniques can be employed on real designs.

KW - Distributed parallel simulation and synchronization

UR - https://www.scopus.com/pages/publications/11844269859

M3 - 会议文章

AN - SCOPUS:11844269859

SN - 1027-2658

VL - 16

SP - 404

EP - 409

JO - Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems

JF - Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems

M1 - 439-179

T2 - Proceedings of the 16th IASTED International Conference on Parallel and Distributed Computing and Systems

Y2 - 9 November 2004 through 11 November 2004

ER -

Techniques to reduce synchronization in distributed parallel logic simulation

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