Technology CAD of SiGe-heterojunction field effect transistors

S. Maikap; B. Senapati; C. K. Maiti

doi:10.14429/dsj.51.2230

Technology CAD of SiGe-heterojunction field effect transistors

S. Maikap^*, B. Senapati, C. K. Maiti

^*此作品的通信作者

Indian Institute of Technology Kharagpur

研究成果: 期刊稿件 › 文章 › 同行評審

1 引文斯高帕斯（Scopus）

摘要

A 2-D virtual wafer fabrication simulation suite has been employed for the technology CAD of SiGe channel heterojunction field effect transistors (HFETs). Complete fabrication process of SiGep-HFETs has been simulated. The SiGe material parameters and mobility model were incorporated to simulate Si/SiGe p-HFETs with a uniform germanium channel having an L_eff of 0.5 μm. A significant improvement in linear transconductance is observed when compared to control-silicon p-MOSFETs.

原文	英語
頁（從 - 到）	195-199
頁數	5
期刊	Defence Science Journal
卷	51
發行號	2
DOIs	https://doi.org/10.14429/dsj.51.2230
出版狀態	已出版 - 04 2001
對外發佈	是

存取文件

10.14429/dsj.51.2230

其它文件與鏈接

Link to publication in Scopus

引用此

@article{f2aa3284de2b4068b6102b01f45e6575,

title = "Technology CAD of SiGe-heterojunction field effect transistors",

abstract = "A 2-D virtual wafer fabrication simulation suite has been employed for the technology CAD of SiGe channel heterojunction field effect transistors (HFETs). Complete fabrication process of SiGep-HFETs has been simulated. The SiGe material parameters and mobility model were incorporated to simulate Si/SiGe p-HFETs with a uniform germanium channel having an Leff of 0.5 μm. A significant improvement in linear transconductance is observed when compared to control-silicon p-MOSFETs.",

keywords = "CMOS circuits, Computer-aided design, Heterojunction field effect transistors, Heterostructure devices, MOSFETs, SiGe p-HFETs, Virtual wafer fabrication simulation",

author = "S. Maikap and B. Senapati and Maiti, {C. K.}",

year = "2001",

month = apr,

doi = "10.14429/dsj.51.2230",

language = "英语",

volume = "51",

pages = "195--199",

journal = "Defence Science Journal",

issn = "0011-748X",

publisher = "Defence Scientific Information and Documentation Centre",

number = "2",

}

TY - JOUR

T1 - Technology CAD of SiGe-heterojunction field effect transistors

AU - Maikap, S.

AU - Senapati, B.

AU - Maiti, C. K.

PY - 2001/4

Y1 - 2001/4

N2 - A 2-D virtual wafer fabrication simulation suite has been employed for the technology CAD of SiGe channel heterojunction field effect transistors (HFETs). Complete fabrication process of SiGep-HFETs has been simulated. The SiGe material parameters and mobility model were incorporated to simulate Si/SiGe p-HFETs with a uniform germanium channel having an Leff of 0.5 μm. A significant improvement in linear transconductance is observed when compared to control-silicon p-MOSFETs.

AB - A 2-D virtual wafer fabrication simulation suite has been employed for the technology CAD of SiGe channel heterojunction field effect transistors (HFETs). Complete fabrication process of SiGep-HFETs has been simulated. The SiGe material parameters and mobility model were incorporated to simulate Si/SiGe p-HFETs with a uniform germanium channel having an Leff of 0.5 μm. A significant improvement in linear transconductance is observed when compared to control-silicon p-MOSFETs.

KW - CMOS circuits

KW - Computer-aided design

KW - Heterojunction field effect transistors

KW - Heterostructure devices

KW - MOSFETs

KW - SiGe p-HFETs

KW - Virtual wafer fabrication simulation

UR - http://www.scopus.com/inward/record.url?scp=0035302288&partnerID=8YFLogxK

U2 - 10.14429/dsj.51.2230

DO - 10.14429/dsj.51.2230

M3 - 文章

AN - SCOPUS:0035302288

SN - 0011-748X

VL - 51

SP - 195

EP - 199

JO - Defence Science Journal

JF - Defence Science Journal

IS - 2

ER -

Technology CAD of SiGe-heterojunction field effect transistors

摘要

存取文件

其它文件與鏈接

指紋

引用此