TY - JOUR
T1 - Testing and evaluation of silicon die strength
AU - Tsai, Ming Yi
AU - Lin, C. S.
PY - 2007/7
Y1 - 2007/7
N2 - In the applications of 3-D packages or stacked die packages, mostly the silicon wafers have to be ground thinner, and then the strengths of the dies from the wafers are needed for assuring good design and reliability of the packages. The purposes of this study are twofold: one is to attempt to develop a new, suitable test method for differentiating the factors that affect the variability of die strength, and the other is to investigate the failure and fatigue strengths of silicon dies. In this paper, a new test method, a plate-on-elastic-foundation test (PEFT) associated with point- or line-loading has been proposed and evaluated. It is found that the PEFT can provide not only a simple, chipping-free test for dummy or real IC chips without limitation of size, but also a (bi-axial) stress field similar to the temperature loading. The strength data of failures on IC and ground surfaces in real IC chips are presented. The good consistency of the die strength data with a minor scatter from both the point- and line-load tests is found for the specimens failed on IC surfaces, but not for the ones failed on the ground surfaces. The inconsistency of strength data from both tests for failure on ground surfaces is due to edge chipping involved. The large scatter is caused by the combined factors of the angle of grinding marks, planes of weakness of material, and loading stress states with uni-axial stress for line-load test and with unequal bi-axial stress for point-load test of rectangular specimens. The surface roughness of the dies (including the IC and ground surfaces) measured by atomic force microscopy is correlated with the failure modes and strengths from the tests. It is found that the silicon die strengths are dominated by the roughness on failure surfaces, and their failure modes always appear cracks along the directions parallel and normal to the edges of the die, which might be the weak plane of the crystal lattice of silicon. The specimens with artificial cracks have been further tested. It has been proved that the die strength dominated by the crack initiation depends on the most severe defect but not on the amount of the defects, and its failure mode is controlled by a special weak plane after the crack initiation. Conclusively, there are four factors to influence die strength: the surface conditions of the die (including grinding-mark direction and surface roughness), the edge crack of the die (so-called chipping created during the cutting process), the weak planes of the crystal lattice of silicon, and, sometimes, different tests with various loading conditions. The fatigue strength of the die is also determined to be about 25% lower than the static one.
AB - In the applications of 3-D packages or stacked die packages, mostly the silicon wafers have to be ground thinner, and then the strengths of the dies from the wafers are needed for assuring good design and reliability of the packages. The purposes of this study are twofold: one is to attempt to develop a new, suitable test method for differentiating the factors that affect the variability of die strength, and the other is to investigate the failure and fatigue strengths of silicon dies. In this paper, a new test method, a plate-on-elastic-foundation test (PEFT) associated with point- or line-loading has been proposed and evaluated. It is found that the PEFT can provide not only a simple, chipping-free test for dummy or real IC chips without limitation of size, but also a (bi-axial) stress field similar to the temperature loading. The strength data of failures on IC and ground surfaces in real IC chips are presented. The good consistency of the die strength data with a minor scatter from both the point- and line-load tests is found for the specimens failed on IC surfaces, but not for the ones failed on the ground surfaces. The inconsistency of strength data from both tests for failure on ground surfaces is due to edge chipping involved. The large scatter is caused by the combined factors of the angle of grinding marks, planes of weakness of material, and loading stress states with uni-axial stress for line-load test and with unequal bi-axial stress for point-load test of rectangular specimens. The surface roughness of the dies (including the IC and ground surfaces) measured by atomic force microscopy is correlated with the failure modes and strengths from the tests. It is found that the silicon die strengths are dominated by the roughness on failure surfaces, and their failure modes always appear cracks along the directions parallel and normal to the edges of the die, which might be the weak plane of the crystal lattice of silicon. The specimens with artificial cracks have been further tested. It has been proved that the die strength dominated by the crack initiation depends on the most severe defect but not on the amount of the defects, and its failure mode is controlled by a special weak plane after the crack initiation. Conclusively, there are four factors to influence die strength: the surface conditions of the die (including grinding-mark direction and surface roughness), the edge crack of the die (so-called chipping created during the cutting process), the weak planes of the crystal lattice of silicon, and, sometimes, different tests with various loading conditions. The fatigue strength of the die is also determined to be about 25% lower than the static one.
KW - Die chipping
KW - Die strength
KW - Electronic packaging
KW - Failure modes
KW - Fatigue strength
KW - Test methods
UR - http://www.scopus.com/inward/record.url?scp=65449130789&partnerID=8YFLogxK
U2 - 10.1109/TEPM.2007.899072
DO - 10.1109/TEPM.2007.899072
M3 - 文章
AN - SCOPUS:65449130789
SN - 1521-334X
VL - 30
SP - 106
EP - 114
JO - IEEE Transactions on Electronics Packaging Manufacturing
JF - IEEE Transactions on Electronics Packaging Manufacturing
IS - 2
ER -