TY - JOUR
T1 - VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation
AU - Lai, Y. K.
AU - Shu, Y. C.
PY - 2001
Y1 - 2001
N2 - In this paper, a novel VLSI architecture of the BLOWFISH block cipher is presented. Based on the loop-folding technique combined with secure modes (ECB, CBC2, CFB2 and OFB2) of operation, the architecture can make data encryption/decryption more efficient and secure. To demonstrate the correctness of our design, a prototype chip for the architecture has been implemented by using 0.35 μ CMOS technology. The chip can achieve an encryption rate of 288 Mb/s and consume 32.7 mW while operating at a 72 Mhz clock rate. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM networks.
AB - In this paper, a novel VLSI architecture of the BLOWFISH block cipher is presented. Based on the loop-folding technique combined with secure modes (ECB, CBC2, CFB2 and OFB2) of operation, the architecture can make data encryption/decryption more efficient and secure. To demonstrate the correctness of our design, a prototype chip for the architecture has been implemented by using 0.35 μ CMOS technology. The chip can achieve an encryption rate of 288 Mb/s and consume 32.7 mW while operating at a 72 Mhz clock rate. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM networks.
UR - http://www.scopus.com/inward/record.url?scp=17044453203&partnerID=8YFLogxK
M3 - 会议文章
AN - SCOPUS:17044453203
SN - 0272-9172
VL - 626
SP - IV57-IV60
JO - Materials Research Society Symposium - Proceedings
JF - Materials Research Society Symposium - Proceedings
T2 - Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications
Y2 - 24 April 2000 through 27 April 2000
ER -