VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation

Y. K. Lai*, Y. C. Shu

*此作品的通信作者

研究成果: 期刊稿件會議文章同行評審

3 引文 斯高帕斯(Scopus)

摘要

In this paper, a novel VLSI architecture of the BLOWFISH block cipher is presented. Based on the loop-folding technique combined with secure modes (ECB, CBC2, CFB2 and OFB2) of operation, the architecture can make data encryption/decryption more efficient and secure. To demonstrate the correctness of our design, a prototype chip for the architecture has been implemented by using 0.35 μ CMOS technology. The chip can achieve an encryption rate of 288 Mb/s and consume 32.7 mW while operating at a 72 Mhz clock rate. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM networks.

原文英語
頁(從 - 到)IV57-IV60
期刊Materials Research Society Symposium - Proceedings
626
出版狀態已出版 - 2001
對外發佈
事件Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, 美國
持續時間: 24 04 200027 04 2000

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