VLSI architectures for median filtering with linear complexity

Erl Huei Lu; Jau Yien Lee; Yawpo Yang

VLSI architectures for median filtering with linear complexity

Erl Huei Lu^*, Jau Yien Lee, Yawpo Yang

^*此作品的通信作者

電機工程學系(含學碩博士班及碩士在職專班)

Chang Gung University

研究成果: 會議稿件的類型 › 論文 › 同行評審

2 引文斯高帕斯（Scopus）

摘要

Two hardware architectures for median filtering with linear complexity are presented in this paper. Both of them are very suitable to implement a filter of large window size owing to their linear hardware complexity. Also, they are suitable for high-speed signal processing because each of them can generate one filtered word in a system clock.

原文	英語
頁面	358-362
頁數	5
出版狀態	已出版 - 1996
事件	Proceedings of the 1996 IEEE Region 10 TENCON - Digital Signal Processing Applications Conference. Part 2 (of 2) - Perth, Aust 持續時間: 26 11 1996 → 29 11 1996

Conference

Conference	Proceedings of the 1996 IEEE Region 10 TENCON - Digital Signal Processing Applications Conference. Part 2 (of 2)
城市	Perth, Aust
期間	26/11/96 → 29/11/96

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Link to publication in Scopus

引用此

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title = "VLSI architectures for median filtering with linear complexity",

abstract = "Two hardware architectures for median filtering with linear complexity are presented in this paper. Both of them are very suitable to implement a filter of large window size owing to their linear hardware complexity. Also, they are suitable for high-speed signal processing because each of them can generate one filtered word in a system clock.",

author = "Lu, {Erl Huei} and Lee, {Jau Yien} and Yawpo Yang",

year = "1996",

language = "英语",

pages = "358--362",

note = "Proceedings of the 1996 IEEE Region 10 TENCON - Digital Signal Processing Applications Conference. Part 2 (of 2) ; Conference date: 26-11-1996 Through 29-11-1996",

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T1 - VLSI architectures for median filtering with linear complexity

AU - Lu, Erl Huei

AU - Lee, Jau Yien

AU - Yang, Yawpo

PY - 1996

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N2 - Two hardware architectures for median filtering with linear complexity are presented in this paper. Both of them are very suitable to implement a filter of large window size owing to their linear hardware complexity. Also, they are suitable for high-speed signal processing because each of them can generate one filtered word in a system clock.

AB - Two hardware architectures for median filtering with linear complexity are presented in this paper. Both of them are very suitable to implement a filter of large window size owing to their linear hardware complexity. Also, they are suitable for high-speed signal processing because each of them can generate one filtered word in a system clock.

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M3 - 论文

AN - SCOPUS:0030312188

SP - 358

EP - 362

T2 - Proceedings of the 1996 IEEE Region 10 TENCON - Digital Signal Processing Applications Conference. Part 2 (of 2)

Y2 - 26 November 1996 through 29 November 1996

ER -

VLSI architectures for median filtering with linear complexity

摘要

Conference

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指紋

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