VLSI design of optimization and image processing cellular neural networks

Detailed design of a currentmode cellular neural network for optimization and image processing is presented. The hardware annealing function is also embedded in the network. It is a paralleled version of fast meanfield annealing in analog networks, and is highly efficient in finding globally optimal solutions for cellular neural networks. The network was designed to perform programmable functions for finegrained processing with annealing control to enhance the output quality. A 5 × 5 prototype chip was fabricated in a 2.0 μm CMOS technology. Since the MOSIS scalable design rules are used, it is also suitable for submicron technologies. For high circuit reliability and compactness purpose, a unit current of 6.0 μA is used. The cell density is 505 cell/cm² and the cell time constant is chosen to be 0.3 μs. From this prototype, a scalable VLSI core of around 50 × 50 neural processors can be integrated on a 1cm² silicon area in a 0.8 μm technology. Experimental results of building blocks and the prototype chip are also presented.