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Voltage-controlled oscillator phase-noise improvement using a GaAs 0.5 νm Pt-buried gate enhancement-mode pHEMT

  • Hsien Chin Chiu*
  • , Po Yu Ke
  • , Che Yu Kuo
  • , Jeffrey S. Fu
  • , Chih Wei Yang
  • , Feng Tso Chien
  • *此作品的通信作者
  • Chang Gung University
  • Feng Chia University

研究成果: 期刊稿件文章同行評審

摘要

This paper presents a voltage-controlled oscillator (VCO) with low phase-noise performance by employing the Pt-buried gate process in enhancement-mode (E-mode) pHEMT technology. After the 4 h stabilization bake process, Pt diffuses into an AlGaAs Schottky layer to form a PtAs2 amorphous layer and native dangling bonds in AlGaAs can be eliminated to improve surface flicker noise. To further evaluate the Pt/AlGaAs interface stability at continuous waveform output operation, the cross-coupled 9 GHz VCO with an E-mode pHEMT (Pt/Ti/Pt/Au gate) and depletion-mode (D-mode) pHEMTs was designed and fabricated in a 0.5 νm gate length 6 inch GaAs wafer simultaneously. The measured phase noise of the Pt-buried gate E-mode pHEMT VCO is -126 dBc Hz -1 at the 1 MHz offset frequency. Compared to the D-mode pHEMT VCO, this novel design achieved an average 10 dB phase-noise improvement at the offset frequency from 100 kHz to 10 MHz.

原文英語
文章編號095003
期刊Semiconductor Science and Technology
24
發行號9
DOIs
出版狀態已出版 - 2009

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